Softwareentwickler/in

Your Role

• Key responsibilities in your new role
• º Full Custom Layout: Execute full-custom IC and block-level layout from schematic to
• tape-out for high-frequency RF blocks and high-speed SerDes components
• º Layout Optimization: Implement precise matching techniques and isolation strategies
• to prevent noise coupling in sensitive analog front-ends
• º Physical Verification: Run and debug full-chip physical verifications including DRC,
• LVS, ERC, and Antenna rule checks
• º Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and
• inductance to ensure signal and power integrity at high frequencies
• º Top-Level Integration: Floorplanning, pad-ring assembly, and final chip integration
• considering ESD, latch-up, and electro-migration (EM) guidelines
• º Leader- & Mentorship: Technical Leadership during project execution and mentor
• junior layout engineers within the team

Ihr Profil

Your Profile

• Qualifications and skills to help you succeed
• º Education: A university (of applied sciences) degree in Electrical Engineering or
• comparable
• º Experience: hands-on experience in CMOS and FinFET semiconductor technologies
• º RF Expertise: Proven track record in analog/RF IC layout including high-speed
• interfaces (e.g., PCIe, Ethernet, USB, or custom SerDes) operating at multi-gigabit data
• rates
• º Tool Expertise: High proficiency with industry-standard EDA tools (Cadence Virtuoso,
• Siemens Calibre, ...)
• º Problem-Solving: Excellent analytical skills to independently debug complex layout
• and physical verification issues
• º Communication Skills: Excellent communication skills to bridge technical gaps across
• global, multi-disciplinary engineering teams
• º Leadership & Teamwork: Strong leadership skills with the ability to guide, motivate,
• and coordinate small layout team during the project execution and to collaborate closely

with RF Design Engineers

• º Languages: Fluent in English
• Apply to: <[email hidden]>