Sr Principal Analog Design Engineer

About onsemi onsemi is a global leader in intelligent power and sensing technologies, enabling automotive, industrial, and cloud customers to build safer, more sustainable, and more energy-efficient systems. The Treo™ platform is central to onsemi’s next-generation automotive and industrial SoC strategy, delivering scalable, safety-focused power, clock, and system management solutions. Role Overview We are seeking a Sr Principal Analog Design Engineer to provide technical leadership and hands-on design expertise for analog IP supporting the power, clock, and error management subsystems of the onsemi Treo™ platform . This role is ideal for a highly experienced analog designer who has successfully delivered production-proven IP , understands automotive-grade quality and functional safety , and is comfortable operating in a digital-on-top SoC integration environment . The role combines deep technical ownership with mentoring, design review, and quality leadership responsibilities.

Key Responsibilities Analog IP Architecture & Design Architect, design, and deliver analog IP blocks for: Power management (e.g., regulators, monitors, biasing) Clock generation and distribution (e.g., PLLs, oscillators, clock monitors) Error detection, monitoring, and safety-related analog circuitry Drive designs from concept and architecture through schematic, simulation, layout collaboration, and silicon validation . Ensure designs are robust, reusable, and scalable across Treo™ platform derivatives. Production & Quality Ownership Own analog IP blocks that tape out and go to volume production , meeting performance, yield, and reliability targets. Act as a design quality reviewer , providing thorough technical reviews of: Schematics Simulation plans and results Layout considerations Documentation and sign-off readiness Champion best practices in analog design quality , robustness, and documentation. SoC Integration & Cross-Disciplinary Collaboration Deliver analog IP into a digital-on-top SoC flow , supporting: Clear interface definitions Digital control and status visibility Power, clock, and reset integration Work closely with: Digital design teams Verification teams Physical design and layout engineers Systems and product engineering Support top-level integration, bring-up, and debug activities as needed. Automotive & Functional Safety Design and deliver analog IP compliant with automotive-grade requirements , including: Reliability Diagnostic coverage Fault tolerance and detection Apply functional safety concepts (e.g., ISO 26262) at the IP level, including: Safety mechanisms Redundancy and monitoring Support for ASIL-driven requirements Collaborate with safety and systems teams to ensure traceability from requirements to implementation. Technical Leadership & Mentorship Mentor and guide junior and mid-level analog engineers , fostering technical growth and design excellence. Provide hands-on coaching in: Analog fundamentals Debug and failure analysis Design trade-offs and architecture decisions Serve as a technical role model within the Cork analog design organization.

Required Qualifications 12+ years of hands-on analog design experience in IC or SoC development. Proven track record of designing analog blocks that have gone to production in shipped products. Strong experience designing power and/or clock IP blocks for SoC-based products. Demonstrated ability to deliver analog IP into a digital-on-top integration flow . Experience developing automotive-grade IP , with exposure to functional safety requirements . Deep understanding of analog design fundamentals, including: Device physics Noise, stability, and robustness PVT and reliability considerations Strong communication skills and the ability to provide clear, constructive design reviews . Preferred / Plus Qualifications Direct experience supporting ISO 26262 work products at the IP level. Experience with safety diagnostics, monitors, and fault-injection concepts. Familiarity with mixed-signal verification and post-silicon debug. Experience contributing to platform-level IP reuse strategies .