Digital Design Manager

Texas Instruments's Embedded Processing Silicon IP Group is looking for a seasoned technical leader to head IP domain verticals. This role sits at the intersection of deep technical expertise and strategic product thinking — you will own the architecture, roadmap, and execution quality of a focused IP domain that powers TI's next-generation SoC platforms in Embedded Processing product families. The IP team delivers silicon IP blocks that are reused across five major SoC platforms. As a Vertical Lead, you will work directly with Chip Architects and SW Architects to define, develop, and deliver high-quality, reusable IP that enables faster time-to-market and scalable product families. IP Domain Verticals – Where You Can Lead This role is open across the following IP domain verticals. Candidates are expected to have deep expertise in at least one domain and the breadth to collaborate across others: AI Accelerators: Own the architecture and roadmap for neural network inference engines. Drive decisions on compute datapath, memory hierarchy, and scalability across TOPS targets. Define support for INT8/FP8/BF16/FP32 datatypes, vector streaming engines, and hardware-software co-design for Edge AI workloads including transformers, SLMs, and time-series sensor inference. Compute Clusters: Lead architecture of multi-core processor clusters based on ARM Cortex-M/R/A or RISC-V families. Define cluster topology, cache coherency, inter-processor communication, and power/performance trade-offs for embedded real-time and application processing workloads. Security: Define scalable Hardware Security Module architectures spanning low-to-mid-to-high segment products. Own crypto IP selection and integration, secure boot architecture, key management, and certification strategy (ISO 21434, IEC 62443). Drive Caliptra support and reusable security software driver frameworks. Communications & Audio: Architect high-speed and low-power communication IP blocks including USB, Ethernet, CAN-FD, LIN, and audio subsystems. Define interface specifications, PHY integration strategies, and protocol compliance requirements for industrial and automotive applications. Networking: Lead IP architecture for on-chip networking fabrics, Ethernet switch subsystems, TSN (Time-Sensitive Networking), and functional safety-aware interconnects. Define QoS, traffic shaping, and real-time determinism requirements for industrial automation and automotive networking. Control & Sense: Own architecture of analog-digital interface IP including ADCs, DACs, comparators, timers, PWM engines, and sensor interface blocks. Define mixed-signal integration strategies, calibration architectures, and functional safety (IEC 61508 / ISO 26262) compliance for motor control and industrial sensing applications. Platform & Infrastructure: Define the foundational SoC infrastructure IP: power management, clock/reset distribution, DMA engines, memory controllers, debug/trace subsystems, and boot infrastructure. Drive reuse strategies and platform IP standardization across product families. Key Responsibilities Own the end-to-end architecture and IP roadmap for your assigned domain vertical, from concept through silicon delivery. Define architectural requirements and micro-architecture specifications for IP blocks; lead trade-off analysis across PPA (Power, Performance, Area) vectors. Translate high-level market and system requirements into implementable HW and SW feature definitions. Assess cost, power, security, and functional safety implications of architectural choices at the IP and SoC level. Drive IP reuse strategy across multiple SoC platforms Engage with external IP vendors, standards bodies, and ecosystem partners as needed. Represent the vertical in cross-functional planning forums and communicate architectural vision to senior leadership.

Minimum requirements: 8–15 years of relevant experience in SoC architecture, IP design, or digital/mixed-signal design. Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. Demonstrated expertise in at least one of the IP domain verticals listed above. Strong understanding of SoC architecture principles: system partitioning, bus fabrics, power domains, clock/reset, and memory subsystems. Proven ability to define architectural specifications and lead IP development from concept to tape-out. Experience with ARM Cortex-M/R/A processor families and/or RISC-V architectures. Solid foundation in hardware/software interface design and embedded system integration. Strong analytical and problem-solving skills with the ability to make sound judgments based on early or partial data.