ASIC II - AMZ27538.3

Employer: Annapurna Labs (U.S.) Inc.Position: ASIC II - AMZ27538.3Location: Cupertino, CAMultiple Positions Available:Help provide a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers <businesses.Design> and optimize hardware in data centers including AWS Inferentia.Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.Execute lint and clock domain crossing quality checks to ensure design integrity.Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.(40 hours / week, 8:00am-5:00pm, Salary Range $157300 - $212800)<Amazon.com> is an Equal Opportunity – Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation#0000