Senior Physical Design Engineer

Join our ASIC implementation team as a Senior Physical Design Engineer. In this role, you will be responsible for the physical implementation of complex digital SoC designs, targeting advanced process nodes for 5G, IoT, and LEO satellite communications applications. You will lead the physical design implementation from floorplanning through GDSII sign-off, collaborate with various teams, and contribute to physical design methodology development. Candidates should have a minimum of 8 years of experience in physical design of complex digital ASICs or SoCs, with expertise in Cadence Innovus and a solid understanding of low-power design techniques.

• Lead the physical design implementation process from floorplanning through GDSII sign-off for complex SoC blocks and full-chip designs.
• Collaborate with cross-functional teams to analyze and resolve timing violations, conduct physical verification, and ensure design rule compliance.
• Develop and maintain physical design scripts, flows, and automation in Tcl/Python, and contribute to physical design methodology development.

• Strong experience in floorplanning, power planning, placement, CTS, and routing for multi-million gate designs
• Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug
• Proficiency in scripting (Tcl, Python) for flow development and automation
• Deep knowledge of timing-driven physical design and working with STA engineers for timing closure
• Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2
• Strong problem-solving skills and attention to detail in a deadline-driven environment
• Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs
• Solid understanding of low-power design techniques (clock gating, power domains, UPF/CPF)
• Experience with advanced process nodes and associated PDK constraints
• Experience with 7nm or sub-7nm process nodes
• Exposure to custom digital or mixed-signal IC physical design
• Experience with hierarchical physical design flows for very large SoCs
• Familiarity with signal integrity analysis tools and methodology
• Background in satellite, 5G, or IoT chip design