Senior Physical Design Engineer

Join our team as a Senior Physical Design Engineer, where you will play a crucial role in the physical design of our SoC products. You will be responsible for implementing physical design from RTL to GDSII, building floorplans, performing block-level place and route, generating and implementing ECOs, integrating DFT into physical design, and running physical design verification. You will collaborate closely with various teams to ensure cohesive design implementation and successful project tapeouts. Enjoy a range of benefits, including an annual bonus, recognition for your contributions, subsidized health insurance, retirement programs, paid time off, a hybrid work model, and opportunities for personal and professional development.

• Contribuer à toutes les phases de la conception physique, de RTL à la livraison de GDSII.
• Implémenter la conception physique au niveau du bloc SoC, y compris la planification du sol, le placement des macros et l'optimisation.
• Collaborer étroitement avec les équipes d'architecture, de conception frontend, de DV et d'emballage pour assurer une mise en œuvre cohérente de la conception.

• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at block level
• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough
• Proficiency in writing Linux shell scripts in Perl, TCL, and Python
• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes
• Real chip tapeout experience in 7nm and/or below with a successful signoff track record
• Exposure to DFT is preferred
• Experience in custom place and route
• Ability to work effectively in a dynamic group environment
• MS degree in the above fields with 5+ years of related experience
• High performance and large chip design experience is preferred
• Self-motivated with strong problem-solving and debugging skills
• Exposure to 2.5D/3D packaging is preferred
• BS degree in electrical engineering, computer engineering, or a related field with 5+ years of experience in block or full-chip physical design, or
• Experience in developing and implementing power-grid and clock network at block level