Staff/Senior Staff/ Principal Engineer, Design Verification

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.
• Bachelor’s or master’s degree in Electronics Engineering
• 5-15 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  
• Strong expertise in UVM‑based testbench architecture and development
• Proven experience in metric‑driven verification, including functional and code coverage closure
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
• Experience with directed and constrained‑random verification methodologies
• Experience debugging complex design issues in simulation, emulation, and post‑silicon environments
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting
• Strong analytical, problem‑solving, and communication skills

Preferred/Plus Qualifications

• Hands‑on experience using AI/ML‑based verification tools for:
• Coverage gap analysis
• Test stimulus optimization
• Regression triage and coverage acceleration
• Scripting expertise in Python, Perl, or TCL for automation and analytics
• Exposure to formal verification and hybrid formal‑simulation flows
• Familiarity with high‑speed or complex IPs, such as:
• H.264
• Security, debug, or safety‑crititical

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our  Diversity & Inclusion Statement .