DFT Engineer

Qualification: BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement .
• Hands-on experience in MBIST insertion and simulation .
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500 .
• Experience with RTL and netlist-based DFT flows .
• Experience in DFT simulation with and without SDF .
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization .
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor .
• Good scripting skills in Perl and TCL .
• Exposure to Static Timing Analysis (STA) is preferred.

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams .
• Support DFT activities through tapeout and silicon bring-up .

Ideal Profile: Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up .