Senior NVM Digital Designer

We are hiring an experienced digital designer to work on the next generation NVM (non-volatile memory) controller for analog compute-in memory technology. The candidate will be responsible for the design, development, and verification of NVM IP and digital controllers for Mythic’s product architecture. This role collaborates closely with circuit, digital, compiler, firmware, and software teams to define NVM controller architecture, develop and validate behavioral models, and improve RTL design and verification methodologies.

What you'll do

Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries

Contribute to next generation NVM digital controller

Responsible for NVM digital controller design, definition, interface, and communications

Work with NVM circuit designers for RNM, functional, and verilog models of NVM circuits

Drive verifications of RNM and functional models of NVM circuits

Participate in design reviews and contribute to improving RTL coding practices and methodologies.

Work closely with digital, compiler, firmware, and software team to define NVM controller architecture

What you'll bring

Ph.D. or MS degree in EE or related 3+ years industrial experience in RTL design, microarchitecture, and architecture development.

Hands-on experience in full chip digital simulation setup, debugging, and verification

Familiar and hands-on experience on NVM (NOR / NAND / similar) voltage operation and/or programming algorithms, and timing diagram is a plus

Understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies) is a plus.

Experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic is a plus.

Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling

Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.

Familiarity with timing constraints, physical design considerations, and EDA flows.

Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.

Excellent communication skills, ability to work well across multi-functional teams