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存储器电路设计工程师-Memory Circuit Design Engineer(J20258)

ChangXin Memory (CXMT) · 安徽省·合肥市, 上海市, 日本

Other EngineeringImported listingfull-time3 months ago

About The Role

  • 1.存储区版图设计与面积优化： 基于存储器电路完成存储器内核版图的设计与实现，规划存储区内核版图，配合电路工程师压缩面积并优化版图布局，提升芯片性能；
  • 2.版图物理验证： 主导存储器内核版图的物理验证，完成DRC、LVS、ERC等全流程检查，确保版图可制造性与功能一致性；
  • 3.跨团队协同迭代： 与电路设计工程师紧密协作，根据仿真反馈迭代优化版图，包括匹配、对称性及EM/IR分析。
  • 1.教育背景与专业知识：本科及以上学历，微电子、电子工程或相关专业；
  • 2.专业技能与资格：具备存储器版图设计能力，熟悉版图物理验证流程，能借助EDA工具完成DRC/LVS/ERC验证；
  • 3.行业与专业经验：1年以上存储器版图设计经验，有先进工艺下模拟版图经验者优先；
  • 4.项目/任务成果：主导或深度参与过至少1款存储芯片的内核版图设计项目，完成从版图设计到物理验证的全流程闭环；
  • 5.其他要求：具有跨团队协作能力，能与电路工程师高效沟通，具备英语或日语阅读能力者优先。

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