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版图设计工程师-Layout Design Engineer(J13201)

ChangXin Memory (CXMT) · 安徽省·合肥市

Other EngineeringImported listingfull-time5 months ago

About The Role

  1. 版图设计与验证：主导版图设计和验证，使用LVS、DRC、LVL等验证工具完成全流程检查，确保版图数据准确；
  2. Testkey设计与优化：参与Testkey（TEG）设计优化，具备TEG版图优化、功能模块开发及测试结构设计经验；
  3. 跨部门协作与交付：与设计和工艺工程师充分沟通，确保项目按时准确交付。
  • 1.教育背景与专业知识：硕士及以上学历，半导体、物理学、材料科学与工程或微电子等相关专业；
  • 2.行业与专业经验：3年以上半导体行业经验，在版图设计和验证上有丰富经验；
  • 3.专业技能与资格：掌握Cadence Virtuoso或华大Aether等EDA工具，熟悉半导体测试流程（如晶圆测试、可靠性测试）；
  1. 项目/任务成果：主导或深度参与过至少2项TEG设计或版图验证项目，并成功交付；
  2. 其他要求：具有良好的团队协作能力和横向沟通能力。

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