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DDR数字设计高级工程师-Senior DDR Digital Design Engineer(J19592)

ChangXin Memory (CXMT) · 上海市

Other EngineeringSenior LevelImported listingfull-time5 months ago

About The Role

  1. 模块级架构设计：针对前沿工艺和规格，主导高速存储接口PHY IP的模块级规格制定与架构实现，确保设计符合性能与功耗目标；
  2. Chiplet接口开发：推动Chiplet接口模块的规格制定与架构实现，拉通跨模块协同，确保接口兼容性与数据完整性；
  3. 高速内存接口实现：参与高速内存接口的高层次产品规范与微架构定义，主导RTL编码、LINT检查及健全性测试，确保代码质量与功能正确；
  4. 硬件验证与调试：支持硬件FPGA设计及bring-up，协同验证团队进行实验室调试，推动问题闭环；
  5. 系统性能优化：与软件团队和/或客户合作，识别并解决系统级问题，主导调试与系统性能调优，达成设计指标。
  6. 教育背景与专业知识：通信、电子工程或计算机工程专业硕士及以上学历，具备扎实的数字电路设计基础；
  7. 专业技能与资格：能使用Verilog HDL完成复杂逻辑设计，能使用综合和时序分析等EDA工具完成设计验证；
  8. 行业与专业经验：5年以上ASIC/FPGA设计经验，熟悉ASIC开发流程，有DDR高速接口设计经验者优先；
  9. 项目/任务成果：具备从零搭建完整数字系统设计流程的能力，主导过至少一个数字IP或接口模块的完整开发；
  10. 其他要求：具有独立分析与解决问题的能力，能主动推动跨团队协作并完成复杂设计任务。

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