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DDR PHY模拟设计工程师/专家-DDR Physical Layer Analog Design Engineer/Expert(J18333)

ChangXin Memory (CXMT) · 上海市, 安徽省·合肥市, 北京市

Other EngineeringImported listingfull-time5 months ago

About The Role

  1. 高速模拟电路设计：主导DDR PHY中PLL/DLL/TXRX/ODT等高速模拟电路的架构设计与性能优化，输出满足指标的设计方案；
  2. 信号完整性设计：分析高速信号传输链路，设计均衡电路补偿信道损耗，通过仿真验证信号眼图满足JEDEC规范；
  3. 工艺适配与版图实现：基于工艺特点调整电路参数，指导版图工程师完成物理设计，解决寄生效应及PVT波动带来的影响；
  4. 仿真与验证闭环：搭建仿真平台完成前仿/后仿验证，制定测试方案并配合ATE调试，分析测试数据以定位并优化设计缺陷；
  5. 设计文档与技术归档：撰写并维护设计文档，沉淀关键设计经验与验证报告。
  6. 教育背景与专业知识：硕士及以上学历，微电子/集成电路/物理电子学等相关专业，具备扎实的半导体器件与模拟电路理论基础；
  7. 专业技能与资格：能使用Cadence/Synopsys等EDA工具完成电路设计与仿真，具备SI/PI分析能力；
  8. 行业与专业经验：5年以上DDR PHY或高速模拟接口设计经验，有DDR5、LPDDR6或类似协议的产品量产经历；
  9. 项目/任务成果：主导过至少一款DDR PHY芯片中关键模拟模块（如PLL、TX、RX）从设计到验证的完整流程；
  10. 其他要求：具有系统化思维，能主动识别技术风险并推动问题闭环，能在跨团队协作中高效对齐目标。

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