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异构集成设计工程师-Heterogeneous Integration Design Engineer(J18206)

ChangXin Memory (CXMT) · 安徽省·合肥市

Other EngineeringImported listingfull-time5 months ago

About The Role

  1. 主导 HB(1+1 F2F) 和 CoW 1+1 HB 的 align/OVL/bonder tree 及标记设计，优化工艺精度；
  2. 制定逻辑框架（logic frame）布局规则，完成 T/O 技术调研表（T/O survey form）输出；
  3. 设计 TEG(testkey)、Seal ring、TTV/THK pad 及切割路径（dicing design），确保芯片物理可靠性；
  4. 开发 frame/chip dummy 填充方案，提升可制造性（DFM）与良率；
  5. 设计 TV spider mask 并主导 MV 产品掩模就绪（mask readiness）全流程；
  6. 执行 GDS/JDV 校验报告（check report），确保设计数据与工艺匹配性；
  7. 跨部门协同与技术规范文档梳理。
  8. 硕士及以上学历，微电子/材料/机械工程专业；
  9. 3年以上异构集成设计经验，熟悉 CoWoS异构集成技术；
  10. 熟悉OVL/bonder mark 设计规范与TEG 结构设计及切割工艺仿真；
  11. 熟练掌握光刻掩模（spider mask）设计流程和GDS 物理验证与 JDV 调试；
  12. 思维开阔，有创新精神。

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