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版图设计工程师-Layout Design Engineer(J10335)

ChangXin Memory (CXMT) · 上海市

Other EngineeringImported listingfull-time5 months ago

About The Role

  1. 版图设计实现：根据集成电路原理图完成版图设计，确保电路功能与性能的准确实现；
  2. Floorplan规划与性能优化：规划版图的Floorplan，与电路设计工程师协作，优化版图以达成电路性能最优化；
  3. 物理验证闭环：完成版图物理验证，包括DRC、LVS、ERC等，确保版图设计符合工艺与设计要求。
  4. 教育背景与专业知识：本科及以上学历，微电子、集成电路等相关专业；
  5. 专业技能与资格：熟悉全定制设计流程的版图设计、物理验证及参数提取，能熟练使用Cadence、Synopsys、StarRC、DRC/LVS等全定制设计EDA工具；
  6. 行业与专业经验：具备集成电路设计验证从业经验，有3D Layout经验者优先，精通Wafer on Wafer工艺的Layout设计；
  7. 其他要求：具有良好的学习能力、沟通能力和团队合作精神，能协同电路设计工程师完成优化目标。

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