ASIC Layout Engineer

As ASIC Layout Engineer you generate the block and Chip layouts based on analog circuits / schematics in our Advanced Electronics & Semiconductor Solutions (AESS).
The layout engineer chooses appropriate methods to reach robust DRC compliant layout with efficient area utilization. Layout engineer works very closely with the analog circuit designer.
Tasks
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Creating and integrating analog layouts on block and top level
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Floor planning, pin placement, parasitic extraction
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Support design engineer to reach speed, area, power, DFM & ESD/EMV requirements
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DRC,LVS & Tape out support
Your profile
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Master of Science / PhD in Electrical Engineering / Microelectronics / Physics or similar
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Bachelor degree in electronics engineering
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+2 years of layout design experience
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Good knowledge in area of analog circuit layout
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Nice to have experience in doing layouts in BCD technology (Technologies: 65 - 180nm)
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Good knowledge in the area of deep sub micron effects (parasitics, coupling, matching etc.)
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Basic understanding of layout tools (design, DRC, LVS, Extraction)
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Basic knowledge of analog circuit design
Languages
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Fluent English
Capabilities
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Must be a team player with good communication and negotiation skills
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Customer focus (anticipates and understands the customers‘ needs)
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Motivation and inspiration (operates with integrity and demonstrates dynamism)
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Taking initiative