Principal FW/SW Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><span data-contrast="none"><span data-ccp-parastyle="heading 1">Principal Engineer – Embedded Firmware & Software</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":360,"335559739":80}"> </span></p>
<p><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"276295ed-5df2-5456-988c-5fdbab071054|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"180",335559738,"180",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",469775498,"Body Text",469778324,"Body Text"]}">Location: Toronto or Ottawa, Ontario (Remote)</span></span> <br><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Travel: Occasional travel to Astera Labs’ San Jose headquarters, </span><span data-ccp-parastyle="First Paragraph">approximately twice</span><span data-ccp-parastyle="First Paragraph"> per year, for chip bring-up and project coordination</span></span> <br><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Employment: Full-time</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="Body Text">Role Overview</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><span data-contrast="auto"><span data-ccp-parastyle="Body Text">Join Astera Labs’ Signal Connectivity Engineering team as a Principal </span><span data-ccp-parastyle="Body Text">Engineer</span><span data-ccp-parastyle="Body Text"> shaping the firmware and software that makes advanced connectivity products adaptive, reliable, and </span><span data-ccp-parastyle="Body Text">production-ready</span><span data-ccp-parastyle="Body Text">. You will own embedded software across analog connectivity and Ethernet </span><span data-ccp-parastyle="Body Text">retimer</span><span data-ccp-parastyle="Body Text"> platforms, from low-level hardware abstraction and calibration through link management, diagnostics, validation, and customer deployment.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><span data-contrast="auto"><span data-ccp-parastyle="Body Text">This is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior. You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams. Your work will help deliver purpose-built connectivity for rack-scale AI infrastructure as Astera Labs continues to scale.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="Body Text">Key Responsibilities</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><strong><span data-contrast="auto">Firmware Architecture & Product Ownership</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact" data-ccp-parastyle-defn="{"ObjectId":"eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"36",335559738,"36",469775450,"Compact",201340122,"2",134234082,"true",134233614,"true",469778129,"Compact",335572020,"1",469778324,"Body Text"]}">Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Architect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Define software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto">Ethernet, Lab Debug & System Integration</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Debug firmware behavior across Ethernet configurations, link states, and failure modes by tracing interactions among Layer 1 PHY, SERDES, FEC/PCS, MAC, </span><span data-ccp-parastyle="Compact">retimer</span><span data-ccp-parastyle="Compact">, and gearbox components.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Investigate register accesses, embedded SDK behavior, link state machines, PHY telemetry, logs, and real-hardware measurements to </span><span data-ccp-parastyle="Compact">identify</span><span data-ccp-parastyle="Compact"> root causes and deliver targeted fixes.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Partner with system validation to develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Support </span><span data-ccp-parastyle="Compact">customer</span><span data-ccp-parastyle="Compact"> bring-up, field issue triage, and deployment readiness in collaboration with applications, </span><span data-ccp-parastyle="Compact">platform</span><span data-ccp-parastyle="Compact">, and silicon teams.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto">Technical Leadership & Collaboration</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Set technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Serve as a technical authority for mixed-signal firmware, analog control behavior, Ethernet physical-layer debug, and hardware/software integration.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Lead design reviews, implementation, code reviews, and difficult debug efforts across firmware, analog, silicon, systems, validation, and applications teams.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Mentor engineers and help build the team through recruiting, onboarding, and technical development; </span><span data-ccp-parastyle="Compact">people</span><span data-ccp-parastyle="Compact"> management or a senior technical-lead path may be available as the organization grows.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Basic Qualifications</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Bachelor’s degree in Computer Science</span><span data-ccp-parastyle="Compact">, Electrical Engineering, Computer Engineering, or </span><span data-ccp-parastyle="Compact">a related</span><span data-ccp-parastyle="Compact"> field.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">8–12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Strong embedded C/C++ skills and deep knowledge of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Hands-on experience with Ethernet or high-speed connectivity devices, including Layer 1 PHYs, SERDES, </span><span data-ccp-parastyle="Compact">retimers</span><span data-ccp-parastyle="Compact">, gearboxes, NICs, switches, or related systems.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Solid understanding of physical-layer behavior, link state machines, register-level debug, and hardware/software integration.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience with feedback systems, adaptive algorithms, calibration, or tuning of analog or mixed-signal subsystems.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="9" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Proficiency</span><span data-ccp-parastyle="Compact"> with Microsoft-based development environments and Linux command-line tools, including GCC or Clang, Make, Bash, GDB, and Git.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="10" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Clear written and verbal communication, systematic debugging skills, and the ability to </span><span data-ccp-parastyle="Compact">operate</span><span data-ccp-parastyle="Compact"> effectively in a fast-moving environment with ambiguity.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Preferred Qualifications</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="11" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Master’s degree in Computer Science</span><span data-ccp-parastyle="Compact">, Electrical Engineering, Computer Engineering, or </span><span data-ccp-parastyle="Compact">a related field</span><span data-ccp-parastyle="Compact">.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="12" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Python experience for test automation, debug tooling, data analysis, or lab workflows; hands-on experience with Jenkins and CI/CD infrastructure.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Familiarity with mixed-signal systems and analog signal paths, including ADC/DAC interfaces, sensor readout, transimpedance amplifiers, </span><span data-ccp-parastyle="Compact">transmit</span><span data-ccp-parastyle="Compact"> drivers, CTLE/DFE equalization, CDR/PLL circuits, or thermal control.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="14" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience with </span><span data-ccp-parastyle="Compact">retimer</span><span data-ccp-parastyle="Compact"> or gearbox firmware, SDK/API development, optical modules or pluggable optics, high-speed copper connectivity, Ethernet PHY subsystems, FEC, PMA, or signal-integrity analysis.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="15" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience using oscilloscopes, BERTs, logic analyzers, and other lab equipment; familiarity with FPGA emulation, pre-silicon validation, RTOS, device drivers, coroutines, mentoring, or recruiting.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Salary range is CAD $184,500 to CAD $205,000 depending on experience, level, and business </span><span data-ccp-parastyle="First Paragraph">need</span><span data-ccp-parastyle="First Paragraph">. This role may be eligible for discretionary </span><span data-ccp-parastyle="First Paragraph">bonus</span><span data-ccp-parastyle="First Paragraph">, </span><span data-ccp-parastyle="First Paragraph">incentives</span><span data-ccp-parastyle="First Paragraph"> and benefits.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>