Principal SerDes Bring-up Validation Engineer at Astera

About The Role

&lt;div class=&quot;content-intro&quot;&gt;&lt;p&gt;&lt;span data-teams=&quot;true&quot;&gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at &lt;a id=&quot;menurhut&quot; class=&quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn&quot; href=&quot;http://www.asteralabs.com/&quot; target=&quot;_blank&quot;&gt;www.asteralabs.com&lt;/a&gt;.&lt;/span&gt;&lt;/p&gt;&lt;/div&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;h1 class=&quot;wnfdnti _1ibi0s33y _1ibi0s34u&quot; data-pm-slice=&quot;1 1 []&quot;&gt;Principal SerDes Bring-up Validation Engineer&amp;nbsp;&lt;/h1&gt;
&lt;h2 class=&quot;wnfdnti _1ibi0s33y _1ibi0s34u&quot;&gt;Role Overview&lt;/h2&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.&lt;/p&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;As a hyper-growth company building the purpose-built connectivity that powers rack-scale AI infrastructure, the speed and rigor of our silicon validation directly shape what we can ship. You will partner closely with AMS design, firmware, and system teams to build automated test frameworks, debug complex analog and digital interactions at the physical layer, and deliver clear, data-driven recommendations that influence product direction. This is a high-impact role for a deep technical expert who thrives on hands-on problem solving and mentoring across disciplines.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Key Responsibilities&lt;/span&gt;&lt;/strong&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Design, develop, and execute bring-up plans.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Own end&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;to&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;end post&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;silicon bring up and characterization strategies, translating design/product requirements into measurable test objectives, pass/fail criteria, and schedules.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;2&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Drive design reviews and specification alignment.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Participate in architecture and design&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;3&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Lead hands&lt;/span&gt;&lt;/strong&gt;‑&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;on test execution and bring&lt;/span&gt;&lt;/strong&gt;‑&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;up.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Perform silicon block level bring&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;to&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;data.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;4&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Build and maintain automation frameworks.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;signal test benches.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;5&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Debug and optimize system performance.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;6&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Root&lt;/span&gt;&lt;/strong&gt;‑&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;cause cross&lt;/span&gt;&lt;/strong&gt;‑&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;domain failures.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;level tests; coordinate with design, package, and firmware teams to implement fixes.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;7&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Collaborate with cross&lt;/span&gt;&lt;/strong&gt;‑&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;functional teams.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Work closely with mixed&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;signal design, firmware, system engineering, and manufacturing to deliver detailed results, root&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;cause analyses, optimization recommendations, and formal validation/compliance reports.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;8&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Document findings and improve methodologies.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;9&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Develop test software and platform integrations.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;1&quot; data-list-defn-props=&quot;{&amp;quot;335552541&amp;quot;:1,&amp;quot;335559685&amp;quot;:720,&amp;quot;335559991&amp;quot;:360,&amp;quot;469769226&amp;quot;:&amp;quot;Symbol&amp;quot;,&amp;quot;469769242&amp;quot;:[8226],&amp;quot;469777803&amp;quot;:&amp;quot;left&amp;quot;,&amp;quot;469777804&amp;quot;:&amp;quot;&amp;quot;,&amp;quot;469777815&amp;quot;:&amp;quot;multilevel&amp;quot;}&quot; data-aria-posinset=&quot;10&quot; data-aria-level=&quot;1&quot;&gt;&lt;strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt;Measure and communicate impact.&lt;/span&gt;&lt;/strong&gt;&lt;span data-contrast=&quot;auto&quot;&gt; Define key validation metrics, track coverage and defect trends, and present data&lt;/span&gt;‑&lt;span data-contrast=&quot;auto&quot;&gt;driven conclusions to stakeholders to influence product direction and release decisions.&lt;/span&gt;&lt;span data-ccp-props=&quot;{}&quot;&gt;&amp;nbsp;&lt;br&gt;&lt;br&gt;&lt;/span&gt;
&lt;h2 class=&quot;wnfdnti _1ibi0s33y _1ibi0s34u&quot; data-pm-slice=&quot;1 1 []&quot;&gt;Basic Qualifications&lt;/h2&gt;
&lt;ul class=&quot;wnfdntf&quot;&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Bachelor&#39;s degree in Electrical Engineering, Computer Engineering, or a related field.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers, with a strong understanding of the physical layer and experience developing characterization flows and validating silicon against specifications.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction, paired with exceptional troubleshooting skills and excellent written and verbal communication.&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;h2 class=&quot;wnfdnti _1ibi0s33y _1ibi0s34u&quot;&gt;Preferred Qualifications&lt;/h2&gt;
&lt;ul class=&quot;wnfdntf&quot;&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;MS or PhD in Electrical Engineering or a related field to demonstrate advanced technical depth and specialization.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Hands-on proficiency with signal integrity test equipment and methodologies (BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, advanced probing) and experience designing and debugging lab characterization and demo boards.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Working knowledge of IEEE 802.3 Ethernet standards and experience validating Ethernet PHYs, link training, auto-negotiation, and compliance across speeds and media types.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Practical understanding of serial interfaces such as I2C, I3C, SPI, and UART for device bring-up, firmware interaction, and system integration.&lt;/p&gt;
&lt;/li&gt;
&lt;li class=&quot;wnfdnte _1ibi0s33w&quot;&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Proven ability to translate SI/PI simulation results into testable lab plans and document findings that drive design or process improvements.&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p class=&quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea&quot;&gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;div class=&quot;content-conclusion&quot;&gt;&lt;p&gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.&lt;/p&gt;&lt;/div&gt;