Manager III, Software Development, Verification Team Lead

Annapurna Labs is the team behind AWS Graviton the industry's most advanced ARM-based server SoC.We operate like a start-up with the scale of the world's largest cloud provider.We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.• It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written• It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack• It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality• It closes the loop- from spec to silicon, our verification touches every team and every stage of chip developmentWhat Sets Us ApartAgentic AI is embedded in our workflow- not as an experiment, but as a core part of how we design and verify chipsCutting edge methodologies drive every stage of our verification processRelentless innovation- we don't settle; we actively seek new approaches that raise the bar on silicon qualityWe do classic functional verification (SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionalityPerformance optimization at all levels is at the heart of our targets on top of logical correctness verificationWatch these videos to learn more about Annapurna Labs and the Graviton <project.AWS> re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: <https://www.youtube.com/watch?v=JeUpUK0nhC0AWS> re:Invent 2025 - AWS Graviton <https://www.youtube.com/watch?v=haSHl2BLhm8> Key job responsibilitiesWhat You'll DoDevelop and execute verification plans for IO sub-systems- covering interconnectprotocols, peripheral interfaces, and system-level integrationVerify IO sub-system features including interconnect protocols, various acceleratorsenginesC embedded SW programing and SW debug skillsBuild and maintain UVM-based verification environments for IO sub-systemsVerify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol complianceVerify the IO virtualization SMMU/TLB operations, page table walks, translationgranules, and memory attributes (cache-ability, share-ability)Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditionsDrive coverage closure using functional coverage models, assertion-based verification,and formal methods where applicableContribute to performance verification — ensuring micro-architecturalimplementations meet performance targets alongside correctnessA day in the lifeYou start by reviewing operational metrics and system health dashboards, then connect with your engineers during stand-ups to unblock priorities and provide technical guidance. Midday, you might partner with product management to refine upcoming roadmap items or review a design document from a senior engineer on your team. You regularly hold one-on-ones focused on career growth and development planning. Throughout the day, you shift between strategic planning sessions, cross-team alignment discussions, and writing narratives that communicate your team's vision and progress to leadership.