Senior Engineer RTL Design

Position

Senior Engineer RTL Design

Job Description

Principal Accountabilities

• RTL development for ASIC / FPGA
• Responsible for completion of front end design flow (spec to RTL / Netlist)
• Design, micro architect & do RTL coding, Lint, CDC
• Support existing sustenance designs
• Collaborate with Hardware board design engineers for system level designs, Board level block diagram design and validation of hardware, utilizing the Company specified hardware design tools

Job Complexity

• ● Requires in-depth knowledge and experience
• ● Solves complex problems; takes a new perspective using existing solutions
• ● Works independently; receives minimal guidance
• ● Acts as a resource for colleagues with less experience
• ● Represents the level at which career may stabilize for many years or even until retirement
• ● Contributes to process improvements
• ● Typically resolves problems using existing solutions
• ● Provides informal guidance to junior staff
• ● Works with minimal guidance

Experience / Education

Typically requires 5–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.

Location

IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)

Time Type

Full time

Job Category

Engineering Services