ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years

Become part of our team as an ASIC Engineering Technical Leader in Physical Design, driving next-generation networking chip development. Lead the RTL 2 GDS implementation, focusing on floor planning, place & route, and performance optimisation. Ideal for experienced ASIC engineers with deep expertise in advanced process nodes and large-scale design.