Hardware Engineer (Lead Architect)

Join our team as a Hardware Engineer (Lead Architect) and play a crucial role in defining the silicon and system microarchitecture for our custom unconventional compute platform. You will lead hardware/software co-design efforts, translate transformer architectures into custom mixed-signal compute tiles, and work closely with compiler, RTL, and analog teams. Your expertise in architecture or microarchitecture of high-performance digital systems, along with your proficiency in Python or C++, will be essential in driving our mission to achieve a 100–1000x leap in energy efficiency for generative AI workloads.

• Define the silicon and system microarchitecture for a custom unconventional compute platform, driving architectural trade-offs for energy efficiency.
• Lead hardware/software co-design efforts to break the von Neumann memory wall, translating transformer architectures into custom mixed-signal compute tiles.
• Work closely with compiler, RTL, and analog teams to build performance models, establish microarchitectural specifications, and ensure maximum throughput-per-watt.
• Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL
• Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot
• Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped and directed the structures inside a chip, not just consumed them from the outside
• Experience writing microarchitecture specifications and working closely with RTL engineers through implementation
• A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential
• Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side
• Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it
• Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level