Senior Digital Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview

As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces.

You will work with cross-functional teams to turn complex connectivity requirements into robust, production-ready designs. Your work will span block-level and full-chip development at advanced process nodes and help enable reliable, high-bandwidth connections among CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems. You will help improve product quality, accelerate time to market, and strengthen customer confidence in every release.

Key Responsibilities

Digital Architecture and RTL Implementation

• Develop micro-architecture and implement synthesizable RTL for high-performance PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP.
• Translate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog.
• Own block-level and full-chip design deliverables from specification through implementation and GDS handoff.
• Contribute to designs at advanced process nodes of 16 nm or smaller, including PCIe Gen 6/7, UALink, or UCI-based connectivity where applicable.

Integration, Timing, and Design Quality

• Integrate controller, SerDes, processor, peripheral, and other IP while partnering with RTL, physical design, DFT, verification, and firmware teams.
• Drive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews.
• Support gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities.
• Contribute to top-level integration, floor-planning discussions, PAD planning, and DFT implementation.

Cross-Functional Execution and Debug

• Collaborate with verification and system teams to assess verification completeness, debug design issues, and close implementation gaps.
• Partner with firmware and embedded software teams to define and validate hardware-software interfaces.
• Use Synopsys and Cadence design and analysis tools, along with Python or Perl scripting, to improve design productivity and automation.
• Communicate technical status, risks, and tradeoffs clearly while managing multiple priorities with appropriate ownership and urgency.

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 2 - 5 years of experience in digital design and implementation for complex SoC or silicon products.
• Hands-on experience developing RTL in SystemVerilog or Verilog, including synthesis and timing closure.
• Experience with PCIe or Ethernet controller, bridge, switch, PCS, PHY, or SerDes design and IP integration.
• Experience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies.
• Experience using Python or Perl to automate design, integration, or analysis workflows.
• Ability to collaborate effectively across design, verification, physical design, DFT, firmware, and system teams.
• Authorized to work in Canada.

Preferred Qualifications

• Experience with PCIe or Ethernet SerDes controller or IP-level design, including PCIe Gen 6/7, UALink, or UCI.
• Experience with block-level and full-chip implementation at advanced process nodes of 16 nm or smaller.
• Knowledge of PAD design, DFT, floor planning, and top-level integration.
• Experience developing NIC, switch, storage, or other high-performance connectivity products with embedded firmware interaction.
• Familiarity with continuous integration and continuous delivery workflows for design and verification.
• Experience with FPGA-based prototyping, emulation, or post-silicon debug.
• <span data-contrast=