Senior DFT Engineer

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior DFT Engineer based in India.

This is an opportunity to take ownership of Design-for-Test (DFT) implementation and verification for advanced SoC and ASIC <designs.You>’ll work on complex semiconductor architectures where test coverage, performance, power, and test time are critical design considerations.The role spans scan, ATPG, memory test, boundary scan, IJTAG, timing, verification, and silicon <debug.You>’ll collaborate closely with RTL, verification, physical design, and test engineering teams to solve challenging technical problems.The environment is fast-paced, highly technical, and focused on shipping real silicon rather than lengthy processes or <bureaucracy.You>’ll have meaningful ownership and the opportunity to contribute to products supporting the rapidly expanding AI and high-performance computing infrastructure market.

Accountabilities

• Develop and implement DFT architectures for advanced SoC designs, including scan insertion, scan compression, and hierarchical DFT.
• Generate, optimize, and debug ATPG patterns across fault models such as stuck-at, transition, and path-delay faults, while driving high test coverage and efficient test execution.
• Design, integrate, and verify MBIST controllers, memory repair mechanisms such as BISR, and comprehensive memory test strategies.
• Implement and verify Boundary Scan (BSCAN), JTAG, and IJTAG/IEEE 1687 infrastructure.
• Perform DFT static timing analysis, develop timing constraints, and collaborate with physical design teams to achieve timing closure.
• Execute DFT verification through pre-silicon simulation, gate-level simulation (GLS), and related validation activities.
• Support silicon bring-up, ATE pattern validation, post-silicon debug, and root-cause analysis of DFT-related issues.
• Analyze test coverage and quality metrics, identify gaps, and implement improvements to strengthen overall test effectiveness.
• Work cross-functionally with RTL, verification, physical design, and test engineering teams to troubleshoot and resolve complex DFT challenges.
• Develop scripting and automation solutions to improve DFT implementation, verification, pattern generation, and debug workflows.

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a closely related discipline.
• 4–7 years of hands-on DFT experience within SoC or ASIC development environments.
• Strong practical knowledge of DFT methodologies, including ATPG, scan compression, MBIST, LBIST, BSCAN, JTAG, and IJTAG.
• Experience with industry-standard DFT insertion, ATPG, pattern-generation, verification, and simulation tools.
• Demonstrated experience with silicon bring-up, ATE pattern validation, and post-silicon debug.
• Strong understanding of DFT verification and gate-level simulation workflows.
• Experience with DFT static timing analysis, constraint development, and timing closure is highly valuable.
• Proficiency in scripting and automation using languages such as Python, Tcl, and/or Perl.
• Strong analytical and problem-solving skills, with the ability to diagnose complex technical issues and drive them to resolution.
• Ability to collaborate effectively across multidisciplinary engineering teams while maintaining high technical standards.
• A strong ownership mindset, bias for action, and willingness to work in a fast-moving engineering environment.

Benefits

• Competitive compensation aligned with experience and technical expertise.
• Fully remote work option within India.
• Opportunity to work on advanced semiconductor technology supporting AI and high-performance computing infrastructure.
• Significant technical ownership and exposure to complex SoC/ASIC design challenges.
• Collaboration with experienced semiconductor engineering professionals across global teams.
• Opportunity to contribute to real silicon products and consequential engineering projects.
• Fast-paced environment with minimal bureaucracy and strong emphasis on technical excellence and execution.
• Potential for professional growth through challenging projects and deep technical learning.