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CAD Engineer

NAVITAS SEMICONDUCTOR USA, INC. · Manila, Alabang

External listingfull-time14 days ago

About The Role

DescriptionKey Responsibilities and Duties

Bond shell and BD Drawing Support

Creates and maintains a directory of Bond shell and Build Diagrams for all Navitas products per assembly location

Prepares bond shell for all new packages being developed and to be stored in an assigned folder in the Directory. All revisions to the bond shell and description of change/s must be documented in the same folder.

Prepares single-unit drawing including per layer layout for routable leadframe technology

Generates a weekly report for all requests received including status and completion dates for each request.

3D Model Support

Creates the 3D model for thermal and thermomechanical simulations. Works with Packaging engineer to define the copper alloy and materials in the stacked in preparation for the thermal simulations.

Prepares 3D model for Preliminary and Final Datasheet of Navitas products

Package Outline Drawing Support

Creates and maintains separate directories of Package Outline drawings (POD) for Released Packages and Packages that are still under development. Manages drawing number assignment to differentiate between released and non-released packages

All corresponding changes to the POD must be captured in the revision history. Evidence on design reviews as part of the POD change must be stored in the same directory for future reference.

Aligns all package dimensioning requirement as per acceptable tolerances of a semiconductor component.

QualificationsRequired Qualifications

  • Bachelor’s degree in Engineering or a related technical field.
  • At least 5 years experience in semiconductor package drafting support
  • Apply GDT (Geometric dimensioning and tolerancing) in applicable drawings
  • Excellent communication skills with the ability to collaborate effectively across global, cross-functional organizations.

Preferred Qualifications

  • Advance 2D/ 3D CAD skills (AutoCAD, Solidworks, etc)
  • Familiar with semiconductor package design rules.

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