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ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years
Cisco · Bangalore, India
About The Role
Exciting opportunity for an ASIC Engineering Technical Leader to drive the design and implementation of high-performance ASIC chips. Lead architectural decisions, oversee RTL development, and ensure best industry practices. Ideal for experienced professionals with a strong ASIC background and leadership skills.
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