ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

We are looking for a Design Verification Lead to drive hands-on verification for Cisco's silicon photonics driver integrated circuits. Lead testbench development, write functional tests, and verify control loop and CPU subsystems. Ideal for candidates with 12–16 years’ experience in ASIC design verification and strong expertise in UVM, Python, and C.