ASIC Engineer || RTL Design, Verilog, System Verilog || CDC, Lint || Exp - 4 to 7 years

We are currently hiring a ASIC Engineer to design and develop high-performance ASIC chips, focusing on RTL design and system integration. You will architect solutions, optimise logic for power and area, and contribute to system validation. Ideal candidates have significant ASIC experience and expertise in RTL design within large-scale, high-volume environments.