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Software Engineer 3년 이상

액시언 · 성남시, 경기, 한국

Software DevelopmentExternal listingfull-timeRecently

About The Role

  • ■ Axion은 AI 기반의 혁신적인 반도체 자동설계 및 최적화 솔루션 개발과 산업 전반에 걸친 AI기반 설계 최적화 소프트웨어를 개발하여 글로벌 반도체 시장 및 다양한 산업 영역의 미래를 선도하는 기업입니다.
  • ■ AI Engine을 통해 반도체 설계 프로세스를 혁신하고 있는 저희와 함께 성장할 열정적이고 창의적인 Engineer를 모집합니다.
  • ■ 주요 업무
  • Design, implement, and tune placement and routing algorithms for transistor-level cell layout generation.
  • Formulate layout constraints (design rules, pin access, symmetry, track assignment) as SAT / SMT / ILP / CP models, or develop custom heuristic solvers.
  • Improve solver performance through search-space pruning, symmetry breaking, incremental solving, and parallelization.
  • Measure and improve quality of results (area, routability, DRC-clean rate) against hand-crafted reference layouts.
  • Build benchmark suites and regression harnesses to track QoR and runtime across solver and rule changes.
  • Work with layout and PDK engineers to translate foundry design rules into solver constraints.
  • Document algorithms and contribute to the tool’s algorithmic roadmap.
  • Explore and implement first-order optimization methods (e.g., PDLP) and hardware-accelerated algorithms to scale solver capabilities for massive layout instances
  • ■ 자격요건
  • ㆍ경력 3년 이상
  • ㆍ대학졸업(4년)이상
  • BS / MS / PhD in Computer Science, Operations Research, Mathematics, or a related field with a focus on algorithms, optimization, or scheduling.
  • 3+ years of experience developing optimization, scheduling, or search algorithms in production software, or a PhD with equivalent research engineering depth.
  • Strong C++ with attention to performance and memory; working Python.
  • Solid foundation in combinatorial optimization: ILP / SAT / SMT / CP, graph algorithms, dynamic programming, and local search.
  • Experience profiling and optimizing algorithm runtime and memory on large problem instances.
  • Treats solution quality, runtime, and hardware usage as first-class requirements.
  • ■ 우대사항
  • Experience with EDA placement & routing, layout automation, or VLSI CAD algorithms.
  • Hands-on experience with industrial solvers (Gurobi, CPLEX, OR-Tools, Z3, MiniSat/Kissat), including model tuning.
  • Experience with parallel or distributed search, or solver portfolios.
  • Familiarity with modern large-scale linear programming techniques (e.g., PDLP) and their acceleration via parallel architectures or GPUs (e.g., CUDA).
  • Publications or contest results in optimization, SAT, or EDA (ISPD / ICCAD / DAC contests).
  • Familiarity with semiconductor design rules and standard cell layout.
  • 시차 출퇴근 운영
  • 점심 식사 제공
  • 건강 검진

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