Skip to content
← Back to job listings

Sr. Process Engineer, Chemical Mechanical Planarization

테슬라(Tesla) · 강남구, 서울, 한국

Senior LevelExternal listingfull-timeRecently

About The Role

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. Process engineering is where Terafab technology gets built, atom by atom, and chemical mechanical planarization (CMP) creates the flat surfaces that enable layer stacking.

  • Develop and qualify CMP processes for STI, ILD, metal layers (W, Cu, Co, Ru), and barrier films across all interconnect levels for two concurrent product flows
  • Optimize removal rates, within-wafer uniformity, planarization efficiency, and surface finish through systematic DOE and first-principles analysis of pad, slurry, and conditioning interactions
  • Own post-CMP clean process qualification including brush scrub and chemical clean steps
  • Qualify CMP tools from installation through production readiness, including pad conditioning, slurry delivery, and endpoint detection
  • Analyze processes from a first-principles, physics-based approach to understand and manipulate mechanisms, not just recipes
  • Lead root cause analysis, establish inline metrology and SPC control strategies, and drive systematic yield improvement
  • Support 24/7 manufacturing operations through rotations, on-call availability, and rapid response to critical production issues
  • Drive next-generation CMP slurry formulations and process development
  • BS or MS in Chemical Engineering, Materials Science, Electrical Engineering, Mechanical Engineering, or related technical field
  • 5+ years of hands-on CMP process engineering experience in a semiconductor fab, especially <7nm in a logic, memory, or foundry environment
  • Deep experience with CMP tool qualification (Applied Materials, Ebara, or equivalent), slurry and pad optimization, and process of record (POR) establishment at advanced nodes
  • Proficiency with CMP metrology tools: film thickness measurement, defect inspection, surface roughness measurement (AFM), and dishing/erosion characterization
  • Strong DOE skills and statistical analysis capability (JMP, Python, or R)
  • Ability to work closely and proactively across lithography, etch, thin films, integration, and equipment engineering teams

자세한 사항은 홈페이지 참조

This is an external listing. JobSpring does not represent or verify the employer. Report this listing